Combinational Circuit Using Verilog and OpenLane
Designed and implemented a 5-bit combinational ALU circuit using Verilog HDL and synthesized the design using the OpenLane toolchain with the SkyWater 130 nm Process Design Kit (PDK).
Portfolio
5-Bit CPU Simulation and Verification
Designed and simulated a 5-bit CPU and verified its correctness by executing sample programs stored in ROM.
Build a Large Language Model from Scratch
Implemented a GPT-style language model from scratch, including tokenization, embeddings, attention, transformer blocks, training, and text generation.
Micrograd: A Tiny Autograd Engine
A lightweight automatic differentiation engine implementing reverse-mode autodiff and neural networks with a PyTorch-like API.