Combinational Circuit Using Verilog and OpenLane
The circuit supports two ALU operations:
- NOR
- SHR (Shift Right)
The project demonstrates the complete digital-design workflow, starting from RTL-level Verilog implementation and functional verification to logic synthesis and physical-design processing using an open-source ASIC design flow.
The design was synthesized using OpenLane, targeting the SkyWater SKY130 technology node, providing hands-on experience with the basic stages involved in converting a Verilog hardware description into an ASIC-oriented implementation.
Key features:
- 5-bit input word size
- Verilog-based combinational circuit design
- NOR operation
- Shift-right (SHR) operation
- RTL-level hardware description
- Logic synthesis
- SkyWater 130 nm PDK
- OpenLane ASIC design toolchain
Technologies / Concepts: Verilog HDL, Digital Logic Design, ALU, RTL Design, Logic Synthesis, ASIC Design Flow, OpenLane, SkyWater SKY130 PDK