5-Bit CPU Simulation and Verification
Designed and simulated a 5-bit CPU using a digital logic simulator and verified its correctness by executing sample programs stored in ROM. The project demonstrates the basic internal operation of a processor, including instruction execution, register operations, memory access, arithmetic and logical operations, and program control.
The CPU architecture includes:
- 5 general-purpose registers
- 10-word RAM with a 15-bit word size
- A ROM for storing and executing sample programs
- Arithmetic and logical operations such as ADD, OR, and SHR
- Register-based instructions
- Immediate-value instructions
- Branching and control-flow instructions, including JMP and JL
The processor was tested by loading sample instructions into ROM and observing how the CPU fetched, decoded, and executed each instruction. The simulation was used to verify that register values, memory operations, arithmetic results, and branching behavior worked correctly according to the designed instruction set.
Technologies / Concepts: Digital Logic Design, Computer Architecture, CPU Design, Registers, RAM, ROM, ALU, Instruction Set Architecture, Control Flow